Modeling Of Combinational Circuits Based On Ternary Multiplexer Using VHDL

This paper presents a novel method for defining,analyzing, testing and implementing the basic combinationalcircuitry with VHDL Simulator. This paper shows the potentialof VHDL modeling and simulation that can be applied toTernary switching circuits to verify its functionality and timingspecifications. A novel method is brought out for implementingthe basic combinational circuitry with minimum number ofmultiplexers. It also includes 1-bit and 2-bit position shifter andBarrel shifter. Method of coding is illustrated with respect toblock diagram. An intention is to show how proposed simulatorcan be used to simulate MVL circuits and to evaluate systemperformance. Keywords-MVL; 9-state logic system; Reliability-Unreliabilitymodel; VHDL